Changeset 1006

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Timestamp:
11/18/08 19:50:56 (7 weeks ago)
Author:
liamMT
Message:

- cleaned up USB framework so it's suitable for use outside of Atmel sample code
- updated AT91SAM7X256.h and updated spi and emac code accordingly
- changed heavy makefile to using variables for common paths

Location:
firmware/branches/cpp
Files:
25 modified

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  • firmware/branches/cpp/core/freertos/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h

    r318 r1006  
    22//          ATMEL Microcontroller Software Support  -  ROUSSET  - 
    33//  ---------------------------------------------------------------------------- 
     4//  Copyright (c) 2006, Atmel Corporation 
     5//  
     6//  All rights reserved. 
     7//  
     8//  Redistribution and use in source and binary forms, with or without 
     9//  modification, are permitted provided that the following conditions are met: 
     10//  
     11//  - Redistributions of source code must retain the above copyright notice, 
     12//  this list of conditions and the disclaimer below. 
     13//  
     14//  - Redistributions in binary form must reproduce the above copyright notice, 
     15//  this list of conditions and the disclaimer below in the documentation and/or 
     16//  other materials provided with the distribution.  
     17//  
     18//  Atmel's name may not be used to endorse or promote products derived from 
     19//  this software without specific prior written permission.  
     20//   
    421//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 
    522//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
    … …  
    1532// File Name           : AT91SAM7X256.h 
    1633// Object              : AT91SAM7X256 definitions 
    17 // Generated           : AT91 SW Application Group  05/20/2005 (16:22:29) 
     34// Generated           : AT91 SW Application Group  06/19/2007 (15:41:06) 
    1835//  
    19 // CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// 
    20 // CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005// 
    21 // CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// 
    22 // CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005// 
    23 // CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005// 
    24 // CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// 
    25 // CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// 
    26 // CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// 
    27 // CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005// 
    28 // CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004// 
    29 // CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004// 
    30 // CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004// 
    31 // CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005// 
    32 // CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005// 
    33 // CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// 
    34 // CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// 
    35 // CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// 
    36 // CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// 
    37 // CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// 
    38 // CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// 
    39 // CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005// 
    40 // CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005// 
    41 // CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// 
    42 // CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005// 
    43 // CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// 
     36// CVS Reference       : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006// 
     37// CVS Reference       : /SYS_SAM7X.pl/1.3/Wed Feb  2 15:48:15 2005// 
     38// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005// 
     39// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 14:00:19 2005// 
     40// CVS Reference       : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// 
     41// CVS Reference       : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006// 
     42// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// 
     43// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// 
     44// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005// 
     45// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004// 
     46// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004// 
     47// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004// 
     48// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005// 
     49// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005// 
     50// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// 
     51// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// 
     52// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// 
     53// CVS Reference       : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// 
     54// CVS Reference       : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// 
     55// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005// 
     56// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// 
     57// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// 
     58// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// 
    4459//  ---------------------------------------------------------------------------- 
    4560 
    … …  
    4762#define AT91SAM7X256_H 
    4863 
     64#ifndef __ASSEMBLY__ 
    4965typedef volatile unsigned int AT91_REG;// Hardware register definition 
     66#define AT91_CAST(a) (a) 
     67#else 
     68#define AT91_CAST(a) 
     69#endif 
    5070 
    5171// ***************************************************************************** 
    5272//              SOFTWARE API DEFINITION  FOR System Peripherals 
    5373// ***************************************************************************** 
     74#ifndef __ASSEMBLY__ 
    5475typedef struct _AT91S_SYS { 
    5576  AT91_REG   AIC_SMR[32];   // Source Mode Register 
    … …  
    210231  AT91_REG   VREG_MR;   // Voltage Regulator Mode Register 
    211232} AT91S_SYS, *AT91PS_SYS; 
    212  
     233#else 
     234 
     235#endif 
    213236 
    214237// ***************************************************************************** 
    215238//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller 
    216239// ***************************************************************************** 
     240#ifndef __ASSEMBLY__ 
    217241typedef struct _AT91S_AIC { 
    218242  AT91_REG   AIC_SMR[32];   // Source Mode Register 
    … …  
    237261  AT91_REG   AIC_FFSR;  // Fast Forcing Status Register 
    238262} AT91S_AIC, *AT91PS_AIC; 
    239  
     263#else 
     264#define AIC_SMR         (AT91_CAST(AT91_REG *)  0x00000000) // (AIC_SMR) Source Mode Register 
     265#define AIC_SVR         (AT91_CAST(AT91_REG *)  0x00000080) // (AIC_SVR) Source Vector Register 
     266#define AIC_IVR         (AT91_CAST(AT91_REG *)  0x00000100) // (AIC_IVR) IRQ Vector Register 
     267#define AIC_FVR         (AT91_CAST(AT91_REG *)  0x00000104) // (AIC_FVR) FIQ Vector Register 
     268#define AIC_ISR         (AT91_CAST(AT91_REG *)  0x00000108) // (AIC_ISR) Interrupt Status Register 
     269#define AIC_IPR         (AT91_CAST(AT91_REG *)  0x0000010C) // (AIC_IPR) Interrupt Pending Register 
     270#define AIC_IMR         (AT91_CAST(AT91_REG *)  0x00000110) // (AIC_IMR) Interrupt Mask Register 
     271#define AIC_CISR        (AT91_CAST(AT91_REG *)  0x00000114) // (AIC_CISR) Core Interrupt Status Register 
     272#define AIC_IECR        (AT91_CAST(AT91_REG *)  0x00000120) // (AIC_IECR) Interrupt Enable Command Register 
     273#define AIC_IDCR        (AT91_CAST(AT91_REG *)  0x00000124) // (AIC_IDCR) Interrupt Disable Command Register 
     274#define AIC_ICCR        (AT91_CAST(AT91_REG *)  0x00000128) // (AIC_ICCR) Interrupt Clear Command Register 
     275#define AIC_ISCR        (AT91_CAST(AT91_REG *)  0x0000012C) // (AIC_ISCR) Interrupt Set Command Register 
     276#define AIC_EOICR       (AT91_CAST(AT91_REG *)  0x00000130) // (AIC_EOICR) End of Interrupt Command Register 
     277#define AIC_SPU         (AT91_CAST(AT91_REG *)  0x00000134) // (AIC_SPU) Spurious Vector Register 
     278#define AIC_DCR         (AT91_CAST(AT91_REG *)  0x00000138) // (AIC_DCR) Debug Control Register (Protect) 
     279#define AIC_FFER        (AT91_CAST(AT91_REG *)  0x00000140) // (AIC_FFER) Fast Forcing Enable Register 
     280#define AIC_FFDR        (AT91_CAST(AT91_REG *)  0x00000144) // (AIC_FFDR) Fast Forcing Disable Register 
     281#define AIC_FFSR        (AT91_CAST(AT91_REG *)  0x00000148) // (AIC_FFSR) Fast Forcing Status Register 
     282 
     283#endif 
    240284// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------  
    241 #define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level 
    242 #define   AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level 
    243 #define   AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level 
    244 #define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type 
    245 #define   AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive 
    246 #define   AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive 
    247 #define   AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered 
    248 #define   AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered 
    249 #define   AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive 
    250 #define   AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered 
     285#define AT91C_AIC_PRIOR       (0x7 <<  0) // (AIC) Priority Level 
     286#define   AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level 
     287#define   AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level 
     288#define AT91C_AIC_SRCTYPE     (0x3 <<  5) // (AIC) Interrupt Source Type 
     289#define   AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive 
     290#define   AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive 
     291#define   AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered 
     292#define   AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered 
     293#define   AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive 
     294#define   AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered 
    251295// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------  
    252 #define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status 
    253 #define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status 
     296#define AT91C_AIC_NFIQ        (0x1 <<  0) // (AIC) NFIQ Status 
     297#define AT91C_AIC_NIRQ        (0x1 <<  1) // (AIC) NIRQ Status 
    254298// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------  
    255 #define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode 
    256 #define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask 
     299#define AT91C_AIC_DCR_PROT    (0x1 <<  0) // (AIC) Protection Mode 
     300#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) // (AIC) General Mask 
    257301 
    258302// ***************************************************************************** 
    259303//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller 
    260304// ***************************************************************************** 
     305#ifndef __ASSEMBLY__ 
    261306typedef struct _AT91S_PDC { 
    262307  AT91_REG   PDC_RPR;   // Receive Pointer Register 
    … …  
    271316  AT91_REG   PDC_PTSR;  // PDC Transfer Status Register 
    272317} AT91S_PDC, *AT91PS_PDC; 
    273  
     318#else 
     319#define PDC_RPR         (AT91_CAST(AT91_REG *)  0x00000000) // (PDC_RPR) Receive Pointer Register 
     320#define PDC_RCR         (AT91_CAST(AT91_REG *)  0x00000004) // (PDC_RCR) Receive Counter Register 
     321#define PDC_TPR         (AT91_CAST(AT91_REG *)  0x00000008) // (PDC_TPR) Transmit Pointer Register 
     322#define PDC_TCR         (AT91_CAST(AT91_REG *)  0x0000000C) // (PDC_TCR) Transmit Counter Register 
     323#define PDC_RNPR        (AT91_CAST(AT91_REG *)  0x00000010) // (PDC_RNPR) Receive Next Pointer Register 
     324#define PDC_RNCR        (AT91_CAST(AT91_REG *)  0x00000014) // (PDC_RNCR) Receive Next Counter Register 
     325#define PDC_TNPR        (AT91_CAST(AT91_REG *)  0x00000018) // (PDC_TNPR) Transmit Next Pointer Register 
     326#define PDC_TNCR        (AT91_CAST(AT91_REG *)  0x0000001C) // (PDC_TNCR) Transmit Next Counter Register 
     327#define PDC_PTCR        (AT91_CAST(AT91_REG *)  0x00000020) // (PDC_PTCR) PDC Transfer Control Register 
     328#define PDC_PTSR        (AT91_CAST(AT91_REG *)  0x00000024) // (PDC_PTSR) PDC Transfer Status Register 
     329 
     330#endif 
    274331// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------  
    275 #define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable 
    276 #define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable 
    277 #define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable 
    278 #define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable 
     332#define AT91C_PDC_RXTEN       (0x1 <<  0) // (PDC) Receiver Transfer Enable 
     333#define AT91C_PDC_RXTDIS      (0x1 <<  1) // (PDC) Receiver Transfer Disable 
     334#define AT91C_PDC_TXTEN       (0x1 <<  8) // (PDC) Transmitter Transfer Enable 
     335#define AT91C_PDC_TXTDIS      (0x1 <<  9) // (PDC) Transmitter Transfer Disable 
    279336// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  
    280337 
    … …  
    282339//              SOFTWARE API DEFINITION  FOR Debug Unit 
    283340// ***************************************************************************** 
     341#ifndef __ASSEMBLY__ 
    284342typedef struct _AT91S_DBGU { 
    285343  AT91_REG   DBGU_CR;   // Control Register 
    … …  
    308366  AT91_REG   DBGU_PTSR;   // PDC Transfer Status Register 
    309367} AT91S_DBGU, *AT91PS_DBGU; 
    310  
     368#else 
     369#define DBGU_CR         (AT91_CAST(AT91_REG *)  0x00000000) // (DBGU_CR) Control Register 
     370#define DBGU_MR         (AT91_CAST(AT91_REG *)  0x00000004) // (DBGU_MR) Mode Register 
     371#define DBGU_IER        (AT91_CAST(AT91_REG *)  0x00000008) // (DBGU_IER) Interrupt Enable Register 
     372#define DBGU_IDR        (AT91_CAST(AT91_REG *)  0x0000000C) // (DBGU_IDR) Interrupt Disable Register 
     373#define DBGU_IMR        (AT91_CAST(AT91_REG *)  0x00000010) // (DBGU_IMR) Interrupt Mask Register 
     374#define DBGU_CSR        (AT91_CAST(AT91_REG *)  0x00000014) // (DBGU_CSR) Channel Status Register 
     375#define DBGU_RHR        (AT91_CAST(AT91_REG *)  0x00000018) // (DBGU_RHR) Receiver Holding Register 
     376#define DBGU_THR        (AT91_CAST(AT91_REG *)  0x0000001C) // (DBGU_THR) Transmitter Holding Register 
     377#define DBGU_BRGR       (AT91_CAST(AT91_REG *)  0x00000020) // (DBGU_BRGR) Baud Rate Generator Register 
     378#define DBGU_CIDR       (AT91_CAST(AT91_REG *)  0x00000040) // (DBGU_CIDR) Chip ID Register 
     379#define DBGU_EXID       (AT91_CAST(AT91_REG *)  0x00000044) // (DBGU_EXID) Chip ID Extension Register 
     380#define DBGU_FNTR       (AT91_CAST(AT91_REG *)  0x00000048) // (DBGU_FNTR) Force NTRST Register 
     381 
     382#endif 
    311383// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  
    312 #define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver 
    313 #define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter 
    314 #define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable 
    315 #define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable 
    316 #define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable 
    317 #define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable 
    318 #define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits 
     384#define AT91C_US_RSTRX        (0x1 <<  2) // (DBGU) Reset Receiver 
     385#define AT91C_US_RSTTX        (0x1 <<  3) // (DBGU) Reset Transmitter 
     386#define AT91C_US_RXEN         (0x1 <<  4) // (DBGU) Receiver Enable 
     387#define AT91C_US_RXDIS        (0x1 <<  5) // (DBGU) Receiver Disable 
     388#define AT91C_US_TXEN         (0x1 <<  6) // (DBGU) Transmitter Enable 
     389#define AT91C_US_TXDIS        (0x1 <<  7) // (DBGU) Transmitter Disable 
     390#define AT91C_US_RSTSTA       (0x1 <<  8) // (DBGU) Reset Status Bits 
    319391// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------  
    320 #define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type 
    321 #define   AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity 
    322 #define   AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity 
    323 #define   AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space) 
    324 #define   AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark) 
    325 #define   AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity 
    326 #define   AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode 
    327 #define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode 
    328 #define   AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. 
    329 #define   AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. 
    330 #define   AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 
    331 #define   AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. 
     392#define AT91C_US_PAR          (0x7 <<  9) // (DBGU) Parity type 
     393#define   AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity 
     394#define   AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity 
     395#define   AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space) 
     396#define   AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark) 
     397#define   AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity 
     398#define   AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode 
     399#define AT91C_US_CHMODE       (0x3 << 14) // (DBGU) Channel Mode 
     400#define   AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. 
     401#define   AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. 
     402#define   AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 
     403#define   AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. 
    332404// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  
    333 #define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt 
    334 #define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt 
    335 #define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt 
    336 #define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt 
    337 #define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt 
    338 #define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt 
    339 #define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt 
    340 #define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt 
    341 #define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt 
    342 #define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt 
    343 #define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt 
    344 #define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt 
     405#define AT91C_US_RXRDY        (0x1 <<  0) // (DBGU) RXRDY Interrupt 
     406#define AT91C_US_TXRDY        (0x1 <<  1) // (DBGU) TXRDY Interrupt 
     407#define AT91C_US_ENDRX        (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt 
     408#define AT91C_US_ENDTX        (0x1 <<  4) // (DBGU) End of Transmit Interrupt 
     409#define AT91C_US_OVRE         (0x1 <<  5) // (DBGU) Overrun Interrupt 
     410#define AT91C_US_FRAME        (0x1 <<  6) // (DBGU) Framing Error Interrupt 
     411#define AT91C_US_PARE         (0x1 <<  7) // (DBGU) Parity Error Interrupt 
     412#define AT91C_US_TXEMPTY      (0x1 <<  9) // (DBGU) TXEMPTY Interrupt 
     413#define AT91C_US_TXBUFE       (0x1 << 11) // (DBGU) TXBUFE Interrupt 
     414#define AT91C_US_RXBUFF       (0x1 << 12) // (DBGU) RXBUFF Interrupt 
     415#define AT91C_US_COMM_TX      (0x1 << 30) // (DBGU) COMM_TX Interrupt 
     416#define AT91C_US_COMM_RX      (0x1 << 31) // (DBGU) COMM_RX Interrupt 
    345417// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------  
    346418// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------  
    347419// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------  
    348420// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------  
    349 #define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG 
     421#define AT91C_US_FORCE_NTRST  (0x1 <<  0) // (DBGU) Force NTRST in JTAG 
    350422 
    351423// ***************************************************************************** 
    352424//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler 
    353425// ***************************************************************************** 
     426#ifndef __ASSEMBLY__ 
    354427typedef struct _AT91S_PIO { 
    355428  AT91_REG   PIO_PER;   // PIO Enable Register 
    … …  
    389462  AT91_REG   PIO_OWSR;  // Output Write Status Register 
    390463} AT91S_PIO, *AT91PS_PIO; 
    391  
     464#else 
     465#define PIO_PER         (AT91_CAST(AT91_REG *)  0x00000000) // (PIO_PER) PIO Enable Register 
     466#define PIO_PDR         (AT91_CAST(AT91_REG *)  0x00000004) // (PIO_PDR) PIO Disable Register 
     467#define PIO_PSR         (AT91_CAST(AT91_REG *)  0x00000008) // (PIO_PSR) PIO Status Register 
     468#define PIO_OER         (AT91_CAST(AT91_REG *)  0x00000010) // (PIO_OER) Output Enable Register 
     469#define PIO_ODR         (AT91_CAST(AT91_REG *)  0x00000014) // (PIO_ODR) Output Disable Registerr 
     470#define PIO_OSR         (AT91_CAST(AT91_REG *)  0x00000018) // (PIO_OSR) Output Status Register 
     471#define PIO_IFER        (AT91_CAST(AT91_REG *)  0x00000020) // (PIO_IFER) Input Filter Enable Register 
     472#define PIO_IFDR        (AT91_CAST(AT91_REG *)  0x00000024) // (PIO_IFDR) Input Filter Disable Register 
     473#define PIO_IFSR        (AT91_CAST(AT91_REG *)  0x00000028) // (PIO_IFSR) Input Filter Status Register 
     474#define PIO_SODR        (AT91_CAST(AT91_REG *)  0x00000030) // (PIO_SODR) Set Output Data Register 
     475#define PIO_CODR        (AT91_CAST(AT91_REG *)  0x00000034) // (PIO_CODR) Clear Output Data Register 
     476#define PIO_ODSR        (AT91_CAST(AT91_REG *)  0x00000038) // (PIO_ODSR) Output Data Status Register 
     477#define PIO_PDSR        (AT91_CAST(AT91_REG *)  0x0000003C) // (PIO_PDSR) Pin Data Status Register 
     478#define PIO_IER         (AT91_CAST(AT91_REG *)  0x00000040) // (PIO_IER) Interrupt Enable Register 
     479#define PIO_IDR         (AT91_CAST(AT91_REG *)  0x00000044) // (PIO_IDR) Interrupt Disable Register 
     480#define PIO_IMR         (AT91_CAST(AT91_REG *)  0x00000048) // (PIO_IMR) Interrupt Mask Register 
     481#define PIO_ISR         (AT91_CAST(AT91_REG *)  0x0000004C) // (PIO_ISR) Interrupt Status Register 
     482#define PIO_MDER        (AT91_CAST(AT91_REG *)  0x00000050) // (PIO_MDER) Multi-driver Enable Register 
     483#define PIO_MDDR        (AT91_CAST(AT91_REG *)  0x00000054) // (PIO_MDDR) Multi-driver Disable Register 
     484#define PIO_MDSR        (AT91_CAST(AT91_REG *)  0x00000058) // (PIO_MDSR) Multi-driver Status Register 
     485#define PIO_PPUDR       (AT91_CAST(AT91_REG *)  0x00000060) // (PIO_PPUDR) Pull-up Disable Register 
     486#define PIO_PPUER       (AT91_CAST(AT91_REG *)  0x00000064) // (PIO_PPUER) Pull-up Enable Register 
     487#define PIO_PPUSR       (AT91_CAST(AT91_REG *)  0x00000068) // (PIO_PPUSR) Pull-up Status Register 
     488#define PIO_ASR         (AT91_CAST(AT91_REG *)  0x00000070) // (PIO_ASR) Select A Register 
     489#define PIO_BSR         (AT91_CAST(AT91_REG *)  0x00000074) // (PIO_BSR) Select B Register 
     490#define PIO_ABSR        (AT91_CAST(AT91_REG *)  0x00000078) // (PIO_ABSR) AB Select Status Register 
     491#define PIO_OWER        (AT91_CAST(AT91_REG *)  0x000000A0) // (PIO_OWER) Output Write Enable Register 
     492#define PIO_OWDR        (AT91_CAST(AT91_REG *)  0x000000A4) // (PIO_OWDR) Output Write Disable Register 
     493#define PIO_OWSR        (AT91_CAST(AT91_REG *)  0x000000A8) // (PIO_OWSR) Output Write Status Register 
     494 
     495#endif 
    392496 
    393497// ***************************************************************************** 
    394498//              SOFTWARE API DEFINITION  FOR Clock Generator Controler 
    395499// ***************************************************************************** 
     500#ifndef __ASSEMBLY__ 
    396501typedef struct _AT91S_CKGR { 
    397502  AT91_REG   CKGR_MOR;  // Main Oscillator Register 
    … …  
    400505  AT91_REG   CKGR_PLLR;   // PLL Register 
    401506} AT91S_CKGR, *AT91PS_CKGR; 
    402  
     507#else 
     508#define CKGR_MOR        (AT91_CAST(AT91_REG *)  0x00000000) // (CKGR_MOR) Main Oscillator Register 
     509#define CKGR_MCFR       (AT91_CAST(AT91_REG *)  0x00000004) // (CKGR_MCFR) Main Clock  Frequency Register 
     510#define CKGR_PLLR       (AT91_CAST(AT91_REG *)  0x0000000C) // (CKGR_PLLR) PLL Register 
     511 
     512#endif 
    403513// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------  
    404 #define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable 
    405 #define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass 
    406 #define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time 
     514#define AT91C_CKGR_MOSCEN     (0x1 <<  0) // (CKGR) Main Oscillator Enable 
     515#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) // (CKGR) Main Oscillator Bypass 
     516#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time 
    407517// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------  
    408 #define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency 
    409 #define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready 
     518#define AT91C_CKGR_MAINF      (0xFFFF <<  0) // (CKGR) Main Clock Frequency 
     519#define AT91C_CKGR_MAINRDY    (0x1 << 16) // (CKGR) Main Clock Ready 
    410520// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------  
    411 #define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected 
    412 #define   AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0 
    413 #define   AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed 
    414 #define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter 
    415 #define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range 
    416 #define   AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet 
    417 #define   AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet 
    418 #define   AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet 
    419 #define   AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet 
    420 #define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier 
    421 #define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks 
    422 #define   AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output 
    423 #define   AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 
    424 #define   AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 
     521#define AT91C_CKGR_DIV        (0xFF <<  0) // (CKGR) Divider Selected 
     522#define   AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0 
     523#define   AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed 
     524#define AT91C_CKGR_PLLCOUNT   (0x3F <<  8) // (CKGR) PLL Counter 
     525#define AT91C_CKGR_OUT        (0x3 << 14) // (CKGR) PLL Output Frequency Range 
     526#define   AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet 
     527#define   AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet 
     528#define   AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet 
     529#define   AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet 
     530#define AT91C_CKGR_MUL        (0x7FF << 16) // (CKGR) PLL Multiplier 
     531#define AT91C_CKGR_USBDIV     (0x3 << 28) // (CKGR) Divider for USB Clocks 
     532#define   AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output 
     533#define   AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 
     534#define   AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 
    425535 
    426536// ***************************************************************************** 
    427537//              SOFTWARE API DEFINITION  FOR Power Management Controler 
    428538// ***************************************************************************** 
     539#ifndef __ASSEMBLY__ 
    429540typedef struct _AT91S_PMC { 
    430541  AT91_REG   PMC_SCER;  // System Clock Enable Register 
    … …  
    449560  AT91_REG   PMC_IMR;   // Interrupt Mask Register 
    450561} AT91S_PMC, *AT91PS_PMC; 
    451  
     562#else 
     563#define PMC_SCER        (AT91_CAST(AT91_REG *)  0x00000000) // (PMC_SCER) System Clock Enable Register 
     564#define PMC_SCDR        (AT91_CAST(AT91_REG *)  0x00000004) // (PMC_SCDR) System Clock Disable Register 
     565#define PMC_SCSR        (AT91_CAST(AT91_REG *)  0x00000008) // (PMC_SCSR) System Clock Status Register 
     566#define PMC_PCER        (AT91_CAST(AT91_REG *)  0x00000010) // (PMC_PCER) Peripheral Clock Enable Register 
     567#define PMC_PCDR        (AT91_CAST(AT91_REG *)  0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register 
     568#define PMC_PCSR        (AT91_CAST(AT91_REG *)  0x00000018) // (PMC_PCSR) Peripheral Clock Status Register 
     569#define PMC_MCKR        (AT91_CAST(AT91_REG *)  0x00000030) // (PMC_MCKR) Master Clock Register 
     570#define PMC_PCKR        (AT91_CAST(AT91_REG *)  0x00000040) // (PMC_PCKR) Programmable Clock Register 
     571#define PMC_IER         (AT91_CAST(AT91_REG *)  0x00000060) // (PMC_IER) Interrupt Enable Register 
     572#define PMC_IDR         (AT91_CAST(AT91_REG *)  0x00000064) // (PMC_IDR) Interrupt Disable Register 
     573#define PMC_SR          (AT91_CAST(AT91_REG *)  0x00000068) // (PMC_SR) Status Register 
     574#define PMC_IMR         (AT91_CAST(AT91_REG *)  0x0000006C) // (PMC_IMR) Interrupt Mask Register 
     575 
     576#endif 
    452577// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------  
    453 #define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock 
    454 #define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock 
    455 #define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output 
    456 #define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output 
    457 #define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output 
    458 #define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output 
     578#define AT91C_PMC_PCK         (0x1 <<  0) // (PMC) Processor Clock 
     579#define AT91C_PMC_UDP         (0x1 <<  7) // (PMC) USB Device Port Clock 
     580#define AT91C_PMC_PCK0        (0x1 <<  8) // (PMC) Programmable Clock Output 
     581#define AT91C_PMC_PCK1        (0x1 <<  9) // (PMC) Programmable Clock Output 
     582#define AT91C_PMC_PCK2        (0x1 << 10) // (PMC) Programmable Clock Output 
     583#define AT91C_PMC_PCK3        (0x1 << 11) // (PMC) Programmable Clock Output 
    459584// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------  
    460585// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------  
    … …  
    463588// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------  
    464589// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------  
    465 #define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection 
    466 #define   AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected 
    467 #define   AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected 
    468 #define   AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected 
    469 #define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler 
    470 #define   AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock 
    471 #define   AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2 
    472 #define   AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4 
    473 #define   AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8 
    474 #define   AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16 
    475 #define   AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32 
    476 #define   AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64 
     590#define AT91C_PMC_CSS         (0x3 <<  0) // (PMC) Programmable Clock Selection 
     591#define   AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected 
     592#define   AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected 
     593#define   AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected 
     594#define AT91C_PMC_PRES        (0x7 <<  2) // (PMC) Programmable Clock Prescaler 
     595#define   AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock 
     596#define   AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2 
     597#define   AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4 
     598#define   AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8 
     599#define   AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16 
     600#define   AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32 
     601#define   AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64 
    477602// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------  
    478603// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------  
    479 #define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask 
    480 #define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask 
    481 #define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask 
    482 #define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask 
    483 #define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask 
    484 #define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask 
    485 #define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask 
     604#define AT91C_PMC_MOSCS       (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask 
     605#define AT91C_PMC_LOCK        (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask 
     606#define AT91C_PMC_MCKRDY      (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask 
     607#define AT91C_PMC_PCK0RDY     (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask 
     608#define AT91C_PMC_PCK1RDY     (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask 
     609#define AT91C_PMC_PCK2RDY     (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask 
     610#define AT91C_PMC_PCK3RDY     (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask 
    486611// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------  
    487612// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------  
    … …  
    491616//              SOFTWARE API